HCTS299MS Datasheet | Intersil

Features - - - - - - - - - - - - 3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Fanout (Over Temperature Range) -Bus Driver Outputs: 15 LSTTL Loads Military Temperature Range: -55o C to +125o C Significant Power Reduction pared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V LSTTL Input patibility -VIL = 0.8V Max -VIH = VCC/2 Min Input Current Levels Ii ≤ 5µA at VOL, VOH GND 10 - Description The Intersil HCTS299MS is a Radiation Hardened 8-bit shift/ storage register with three-state bus interface capability. The register has four synchronous operating modes controlled by the two select inputs (S0, S1). The mode select, the serial data (DS0, DS7) and the parallel data (IO0 - IO7) respond only to the low to high transition of the clock (CP) pulse. S0, S1 and the data inputs must be one set up time period prior to the clocks positive transition. The master reset (MR) is an asynchronous active low input. The HCTS299MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family with TTL input patibility. 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20 TOP VIEW S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC S1 DS7 Q7 I/O7 I/O5 I/O3 I/O1 CP DS0 Ordering Information PART NUMBER HCTS299DMSR HCTS299KMSR HCTS299D/Sample HCTS299K/Sample HCTS299HMSR TEMPERATURE RANGE -55o C to +125o C -55o C to +125o C +25o C +25o C +25o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack Die DB NA CAUTION: These devices are sensitive to electrostatic...